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1. 산업체 경력 - 24년간 삼성전자 반도체 연구소에서 DRAM Shrink 집적공정(Process Integration) 전문가로서 공정구조, 공정조건, 설계룰을 만들고 설계, 공정, 특성, 신뢰성뿐만 아니라 생산원가 경쟁력을 갖추는데 Project Manager로서 활동하였음.(VP 퇴임) 이후 (주)삼성LED의 품질관리(2년, VP), (주)윌테크놀러지의 MEMS Probe Card 개발(3년, SVP)을 경험하였음. 반도체 공정 Integration, LED 제품과 Probe Card 품질관리, SCM 관리 경험을 활용하여 디지털미디어학과 학생들에게 창의적인 콘텐츠 제작과 멀티미디어 융합, 그 결과 디지털미디어학과 학생들이 산업수요 기반 실무역량을 갖추는데 기여하고자 함. 2. 산학협력중점교원 경력 - 2014.10-2015.8 대전대학교 LINC사업단에서 산학협력중점교원으로 근무하면서 ICT 협의체를 구성 및 운영하였고, 계절학기 현장실습과 ICT 학점연계인턴십을 통하여 회사-학생을 매칭시키고 참여 학생들로 하여금 현장실무역량을 갖추도록 지도하였음. - 2015.9 ~ 현재 아주대학교 디지털미디어학과 산학협력중점교원으로서 협력회사-학생-학과교수 네트워크를 만들고 학생들의 현장실무역량을 높이는데 기여해 왔음. 산학협력협의체를 운영하면서 디지털미디어학과 관련 협력회사를 발굴하고 학생들에게 현장실습 및 인턴십 기회를 확대하여 저학년부터 취창업 진로를 준비하고 기업수요를 피드백하여 미디어교육프로그램 개발에 기여해 왔음. 3. 소프트웨어융합대학 산학협력중점교원 역할 - 디지털미디어학과 디지털콘텐츠 저작 분야 산업체 네트워크를 형성하고 회사-학생-전공교수가 참여하는 산학협력협의체를 운영하면서 기술세미나, 산학기술개발 프로젝트, 표준현장실습 운영 및 취업연계, 취창업 멘토링을 활성화하는데 주도적인 역할을 수행하고자 함. - 2015년부터 진로지도 전문컨설턴트를 지속운영하고 졸업생과 재학생을 연결시켜 실질적인 취업상담을 코디네이션해 왔음. 그 결과 학생이 취업진로를 설정하고, 교과 및 비교과 활동으로 실질적인 전공역량과 포트폴리오를 코칭하고 성공적인 사회진출을 지도하고자 함. |
연구분야 |
Summarized training and social activities during the employment of Samsung 1. 8/1985~1/1987 Semiconductor process engineering training at SSI (Samsung Semiconductor Incorporation), Santa Clara, Ca., USA, Studied thin film process and capacitor integration 2. 3/1994~2/1998 KAIST(Korea Advanced Institute of Science and Technology) Ph.D Course, Major in semiconductor physics with electrical and optical properties in the low dim. Structures 3. 11/19/2003~11/22 TPS(Toyota Production System) Bench Marking, Toured assembly lines and quality systems of Toyota Automobile 4. 11/2/2004 Leadership Course for VP, world-wide competitiveness through product innovations 5. 3/29/2007~3/30 Leadership Course for VP, Structure management for international standard level 6. 10/22/2010 Leadership Course for VP, how to promote creativity 7. 10/2001~12/2008 Device committee in KCS(Korean Conference on Semiconductor), Our department had the presentation of 3-4 papers every year. List of published international papers(Science Citation Index level) 1. Tae-Young Chung and K J Chang, et al., “Optical Properties of ZnSSe/ZnMgSSe Quantum Wells,” Semicon. Sci. Technol. vol. 12, pp. 701-706, 1997. 2. Tae-Young Chung and K J Chang, “Exciton binding energies in GaN/AlGaN quantum-well structures,” Semicon. Sci. Technol. vol. 13, pp. 876-881, 1998. 3. Daeje Chin, Changhyun Kim, Tae-Young Chung, et al., “An Experimental 16-Mbit DRAM with Reduced Peak-Current Noise,” IEEE J. Solid-State Circuits, vol. 24, pp. 1191-1197, Oct. 1989. 4. D. Ha, C. Cho, T.-Y. Chung, et al., “Anomalous Junction Leakage Current Induced by STI Dislocations and Its Impact on Dynamic Random Access Memory Devices,” IEEE Trans. Electron Devices, vol. 46, pp. 940-946, May 1999. 5. Daewon Ha, Dongwon Shin, Taeyoung Chung, et al., “A Cost Effective Embedded DRAM Integration for High Density Memory and High Performance Logic Using 0.15um Technology Node and Beyond,” IEEE Trans. Electron Devices, vol. 47, pp. 1499-1506, July 2000. 6. H. Yoon, G.-W. Cha, C. Yoo, T.-Y. Chung, et al., “A 2.5-V. 333-Mb/s/pin, 1-Gbit, Double-Date-Rate Synchronous DRAM,” IEEE J. Solid-State Circuits, vol. 34, pp. 1589-1599, Nov. 1999. 7. S.H. Shin, S.H. Lee, Y.S. Kim, T.Y. Chung, et al., “Data Retention Time and Electron Characteristics of Cell Transistor According to STI Materials in 90nm DRAM,” JSTS, vol. 3, pp. 68-75, June 2003. 8. Y.K. Park, Y.S. Ahn, K.H. Lee, C.H. Cho, T.Y. Chung, et al, “Novel Robust Structure and High k Dielectric Material for 90 nm DRAM Capacitor,” JSTS, vol. 3, pp-76-82, June 2003. 9. Yong-Sung Kim, Soo-Ho Shin, Tae-Young Chung, et al., “Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60nm Feature Sized DRAM,” JSTS, vol. 6, pp. 61-67, June 2006. 10. Ming Li, Kyoung Hwan Yeo, Sung Dae Suk, Dong-Won Kim, Tae-Young Chung, et al., “Sub-10nm gate-all-around CMOS nanowire transistor on bulk Si substrate,” in Symp. VLSI Technol. Dig. Tech., pp. 94-95, June 2009. 11. Chang Woo Oh, Hyun Jun Bae, Dong-Won Kim, Tae-Young Chung, et al., “Novel thin BOX SOI technology using bulk Si wafer for system-on-chip(SoC) application,” in Symp. VLSI Technol. Dig. Tech., pp. 96-97, June 2009. 12. Sung Dae Suk, Ming Li, Dong-Won Kim, Tae-Young Chung, et al., “Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI,” in Symp. VLSI Technol. Dig. Tech., pp. 142-143, June 2009. |
기타 |
List of registered international patents 1. US5071781, Tae-Young Chung and Kwang-Pyuk Suh, “A METHOD FOR MANUFACTURING A SEMICONDUCTOR” 2. US5120674, Tae-Young Chung and Daije Chin, “STACK CAPACITOR DRAM CELL HAVING INCREASED CAPACITOR AREA” 3. US5183772, Tae-Young Chung, Daije Chin, and Kwang-Pyuk Suh, “MANUFACTURING METHOD FOR DRAM CELL” 4. US5216267, Tae-Young Chung, Daije Chin, and Kwang-Pyuk Suh, “MANUFACTURING METHOD FOR DRAM CEL”L 5. US5378908, Tae-Young Chung and Daije Chin, “STACK CAPACITOR DRAM CELL HAVING INCREASED CAPACITOR AREA” 6. US5422295, Tae-Young Chung, Young-Pil Kim, Young-Je Choi, and Jong-Woo Park, “METHOD FOR FORMING A SEMICONDUCTOR MEMORY DEVICE HAVING A VERTICAL MULTI-LAYERED STORAGE ELECTRODE” 7. US6204162, Tae-Young Chung, Chang-Hyun Cho, and Jae-Goo Lee, “A SELF ALIGNED CONTACT PAD IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME” 8. US6218296, Tae-Young Chung, Dong-Hwa Kwak, and Yoo-Sang Hwang, “PILLAR SHAPED STORAGE NODE OF A CAPACITOR AND METHODS FABRICATING THE SAME” 9. US6229171, Tae-Young Chung, Yoon-Soo Chun, and Yoo-Sang Hwang, “A CAPACITOR OF A SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME” 10. US6242332, Kinan Kim, Tae-Young Chung, and Chang-Hyun Cho, “METHOD FOR FORMING SELF-ALINGNED CONTACT” 11. US6277702, Tae-Young Chung, Yoon-Soo Chun, and Yoo-Sang Hwang, “A CAPACITOR OF A SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME” 12. US6288446, Tae-Young Chung, Dong-Hwa Kwak, and Yoo-Sang Hwang, “PILLAR SHAPED STORAGE NODE OF A CAPACITOR AND METHODS FABRICATING THE SAME” 13. US6403431, Tae-Young Chung and Hyung-Soo Uh, “METHOD OF FORMING IN AN INSULTAING LAYER AN TRENCH THAT EXCEEDS THE PHOTOLITHOGRAPHIC RESOLUTION LIMITS” 14. US6458680, Tae-Young Chung, Jae-Goo Lee, and Gwan-Hyeob Koh, “METHOD FOR FABRICATING CONTACT PADS OF A SEMICONDUCTOR DEVICE” 15. US6613621, Kinam Kim, Tae-Young Chung, et al., “METHOD OF FORMING SELF-ALIGNED CONTACT PADS USING A MAMASCENE GATE PROCESS” 16. US6890841, Yang-Keun Park, Tae-Young Chung, et al., “semiconductor memory device and manufacturing method thereof” 17. US6967150, Tae-Young Chung and Cheol-Ju Yun, “method of forming self-aligned contact in fabricating semiconductor device” 18. US7049203, Tae-Young Chung and Jae-Goo Lee, “semiconductor device having a capacitor and method of fabricating the same” 19. US7056786, Tae-Young Chung, Cheol-Ju Yun, and Chang-Hyun Cho, “self-aligned buried contact in the periphery and method of forming the same(RAS)” 20. US7154144, Tae-Young Chung, Chang-Hyun Cho, Soo-Ho Shin, and Ji-Young Kim, “self-aligned inner gate recessed channel transistor and method of forming the same” 21. US7180118, Tae-Young Chung, Cheol-Ju Yun, et al., “SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE AND METHOD OF MANUFACTURING THE SAME(SAS)” 22. US7205232, Tae-Young Chung and Cheol-Ju Yun, “METHOD OF FORMING A SELF-ALIGNED CONTACT STURCTURE USING A SACRIFICIAL MASK LAYER(ATM)” 23. US7279741, Tae-Young Chung, Chang-Hyun Cho, Soo-Ho Shin, and Yong-Gyu Choi, “SEMICONDUCTOR DEVICE WITH INCREASED EFFECTIVE CHANNEL LENGTH AND METHOD OF MANUFACTUREING THE SAME(ATM)” 24. US3229918, Tae-Young Chung, Chang-Hyun Cho, and Yong-Seok Ahn, “SEMICONDUCTOR MEMORY DEVICE INCLUDING STORAGE NODES AND RESISTORS AND METHOD OF MANUFACTURING THE SAME(ATM)” 25. US7368778, Yong-Sung Kim, Tae-Young Chung, and Jin-Woo Lee, “DRAM HAVING AT LEAST THREE LAYERED IMPURITY REGIONS BETWEEN CANNEL HOLES AND METHOD OF FABRICATING THE SAME” 26. US7388243, Tae-Young Chung, Cheol-Yu Yun, and Chang-Hyun Cho, “self-aligned buried contact in the periphery and method of forming the same(RAS)” 27. US7476585, Tae-Young Chung, Cheol-Ju Yun, et al., “SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE AND METHOD OF MANUFACTURING THE SAME(SAS)” |
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